1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a multilayer wiring structure.
2. Background Art
With an increase in integration density of large-scale integration circuits commonly called micro-processors, memories, or system LSIs, element dimensions such as a gate length of transistors and wiring pitches are being miniaturized. Here, in order to realize miniaturization of wirings, an embedded wiring structure commonly called a Damascene wiring in which wiring trenches are formed in an interlayer insulating film, and copper wirings are formed within the trenches is used in the manufacturing process. A general embedded wiring forming method is realized by forming wiring trenches in an interlayer insulating film, forming a metal film such as a copper film on the entire surface so as to fill the trenches, and removing a metal film formed at the outer side of the wiring trenches by chemical mechanical polishing (CMP).
However, since the polishing rate of CMP is greatly different from a copper film to an interlayer insulating film, a phenomenon of overpolishing of wiring thickness called erosion is likely to occur in positions where wiring density is high. On the other hand, a phenomenon of a decrease in wiring thickness called dishing is likely to occur in positions where a wiring width is large. From these phenomena, there is a problem in that the wiring thickness and the distribution of an interlayer insulating film become uneven depending on a wiring density and a wiring width, and planarity deteriorates. As a result, wiring pattern formation defects are caused, and wiring resistance and interwiring parasitic capacitance increase. Therefore, in the related art, a dummy pattern has been formed in a wiring void so as to decrease a difference in wiring density (refer to Unexamined Japanese Patent Publication No. 60-119749, Unexamined Japanese Patent Publication No. 2005-150389, and U.S. Pat. No. 7,241,558, for example).
Moreover, in recent years, the speed and integration density of semiconductor devices are progressing quickly. In this case, an increase in interwiring capacitance caused by the increase in integration density of wirings is a major cause of hindrance to realizing faster semiconductor devices. The dummy pattern may cause a great problem not only in an interwiring capacitance which it gives to its adjacent wirings but also in an interwiring capacitance which it gives to its upper or lower wirings. Therefore, in the related art, the dummy pattern has been formed while dodging a region overlapping the upper or lower wirings (refer to Unexamined Japanese Patent Publication No. 10-27799, for example).